Extra Instruments, Extra Wafers, & Finest Pellicles In Trade

Though TSMC cannot declare to be the primary fab to make use of excessive UV (EUV) lithography – that title goes to Samsung – they do get to say to be the biggest. Consequently, the corporate has developed vital expertise with EUV through the years, permitting TSMC to refine how they use EUV tooling to each enhance productiveness/uptime, and to chop down on the prices of utilizing the ultra-fine instruments. As a part of the corporate’s European Know-how Symposium this week, they went right into a bit extra element on their EUV utilization historical past, and their progress on additional integrating EUV into future course of nodes.

When TSMC began making chips utilizing EUV lithography in 2019 on its N7+ course of (for Huawei’s HiSilicon), it held 42% of the world’s put in base of EUV instruments, and at the same time as ASML ramped up shipments of EUV scanners in 2020, TSMC’s share of EUV installations actually increased to 50%. And leaping forward to 2024, the place the variety of EUV litho programs at TSMC has elevated by 10-fold from 2019, TSMC is now 56% of the worldwide EUV put in base, regardless of Samsung and Intel ramping up their very own EUV manufacturing. Suffice it to say, TSMC decided to go in laborious on EUV early on, and because of this they nonetheless have the lion’s share of EUV scanners as we speak.

Notably, TSMC’s EUV wafer manufacturing has elevated by an excellent bigger issue; TSMC now pumps out 30 instances as many EUV wafers as they did in 2019. In comparison with the mere 10x enhance in instruments, TSMC’s 30x bounce in manufacturing underscores how TSMC has been in a position to enhance their EUV productiveness, scale back service instances, and fewer instrument downtimes total. Apparently, this has all been completed utilizing the corporate’s in-house developed improvements.

TSMC says that it has managed to extend wafer-per-day-per-tool productiveness of its EUV programs by two instances since 2019. To take action, the corporate optimized the EUV publicity dose and the photoresist it makes use of. As well as, TSMC vastly refined its pellicles for EUV reticles, which elevated their lifespan by 4 instances (i.e., will increase uptime), elevated output per pellicle by 4.5 instances, and lowered defectivity by huge 80 instances (i.e., improves productiveness and will increase uptime). For apparent causes, TSMC doesn’t disclose the way it managed to enhance its pellicle know-how so considerably, however maybe over time the corporate’s engineers are going to share this with academia. 

EUV lithography programs are additionally infamous for his or her energy consumption. So, along with bettering productiveness of EUV instruments, the corporate additionally managed to scale back the ability consumption of its EUV scanners by 24% by means of undisclosed ‘revolutionary vitality saving strategies.’ And the corporate is not performed there: they’re planning to enhance vitality effectivity per wafer per EUV instrument by 1.5 instances by 2030.

Contemplating all of the refinements that TSMC has managed to realize with Low-NA EUV lithography by now, it’s not terribly stunning that the corporate is kind of assured that it could proceed to provide cutting-edge chips sooner or later. Whereas rival Intel has gone all-in on Excessive-NA EUV for his or her future, sub-18A nodes, TSMC is trying to leverage their highly-optimized and time-tested Low-NA EUV tooling as a substitute, avoiding the potential pitfalls of a serious know-how transition so quickly whereas additionally reaping the fee advantages of utilizing the well-established tooling.