Efficiency-Optimized 3nm N3P Course of on Observe for Mass Manufacturing This Yr

As a part of the second leg of TSMC’s spring expertise symposium collection, the corporate provided an replace on the state of its 3nm-class processes, each present and future. Constructing on the again of their current-generation N3E course of, the optical shrink of this course of expertise, N3P, is now on observe to enter mass manufacturing within the second half of 2024. Due to that shrink, N3P is predicted to supply each elevated efficiency effectivity in addition to elevated transistor density over N3E.

N3E in Manufacturing, Yielding Effectively

With N3E already in quantity manufacturing, TSMC is reporting that they are seeing “nice” yields on the second-generation 3nm-class course of word. In response to the corporate, the D0 defect density of N3E is at relative parity with N5, matching the defect price of the older node for a similar level in its respective lifecycle. That is no small feat, given the extra complexities that include creating one final, ever-finer technology of FinFET expertise. So for TSMC’s bleeding-edge clients equivalent to Apple, who simply launched their M4 SoC, that is permitting them to reap the advantages of the improved course of node comparatively shortly.

“N3E began quantity manufacturing within the fourth quarter of final yr, as deliberate,” a TSMC govt mentioned on the occasion. “We have now seen nice yield efficiency on clients’ merchandise, in order that they did go to market as deliberate.”

TSMC’s N3E node is a relaxed model of N3B, eliminating some EUV layers and utterly avoiding the utilization of EUV double patterning. This makes it a bit cheaper to supply, and in some circumstances it widens the method window and yields, although it comes at the price of some transistor density.

N3P on Observe For Second-Half 2024

In the meantime, wanting in the direction of the quick future at TSMC, N3P has completed qualification and its yield efficiency is near N3E, in accordance with the corporate. Being an optical shrink, the N3P node is about to allow processor builders to both enhance efficiency by 4% on the similar leakage or cut back energy consumption by 9% on the similar clocks (beforehand the vary was between 4% ~ 10% relying on design). The brand new node can be set to spice up transistor density by 4% for a ‘blended’ chip design, which TSMC defines as a processor consisting of fifty% logic, 30% SRAM, and 20% analog circuits.

Whereas it seems to be like the unique N3 (aka N3B) could have a comparatively muted lifecycle since Apple has been its solely main buyer, N3E can be adopted by a variety of TSMC’s clients, which incorporates lots of the business’s largest chip designers. 

Since N3P is an optical shrink of N3E, it’s suitable with its predecessor when it comes to IP blocks, course of guidelines, digital design automation (EDA) instruments, and design methodology. In consequence, TSMC expects the vast majority of new tape outs to make use of N3P, not N3E or N3. That is logical as N3P offers larger efficiency effectivity than N3E at a decrease price than N3.

Crucial facet of N3P is that it’s on observe to be manufacturing prepared within the second half of this yr, so anticipate chip designers to undertake it right away. 

“We have now additionally efficiently delivered N3P expertise,” the TSMC govt mentioned. “It has handed qualification and yield efficiency is near N3E. [The process technology] has additionally obtained product buyer tape outs and can begin on manufacturing within the second half of this yr. Due to [PPA advantages] of N3P, we anticipate the vast majority of tape outs on N3 to go to N3P.”